Packing Directed Circuits through Prescribed Vertices Bounded Fractionally

A seminal result of Reed, Robertson, Seymour, and Thomas says that a directed graph has either k vertex-disjoint directed circuits or a set of at most f(k) vertices meeting all directed circuits. This paper aims at generalizing their result to packing directed circuits through prescribed vertices. Even, Naor, Schieber, and Sudan showed a fractional version of packing such circuits. In this paper, we show that a fractionality can be bounded at most fifth: Given an integer k and a vertex subset S, whose size may not depend on k, we prove that either G has a 1/5-integral packing of k disjoint circuits, each of which contains at least one vertex of S, or G has a vertex set X of order at most f(k) (for some function f of k) such that G −X has no such a circuit. We also give an FPT approximation algorithm for finding a 1/5-integral packing of circuits through prescribed vertices. This algorithm finds a 1/5-integral packing of size approximately k in polynomial time if it has a 1/5-integral packing of size k for a given directed graph and an integer k.